In fabricating a semiconductor chip, one of the steps is to generate the layout of the chip. The layout is a graphical representation of the different layers of a semiconductor chip. The layout of a semiconductor chip might show, for example, where metal layers are to be deposited on the chip, or where dopant is to be added to the substrate. The layout of a semiconductor chip is used as a template during the fabrication process.
Because a semiconductor chip contains many complex electrical circuits, a layout is usually generated using computer software. This software allows the designer to prepare the layout by arranging various shapes, referred to as polygons, on the surface of the chip. These polygons, being graphical representations in a computer program, may be manipulated by the layout designer. The polygons can, for example, be moved around to different places in the layout, increased or decreased in size, or copied from one layer of the layout to another.
Semiconductor chips are very small, and space is at a premium. Thus, one typical design goal is to minimize the amount of space that a circuit occupies on the surface of the chip. However, it is also important that the circuit components not be too close together. When a semiconductor chip is fabricated, microscopic quantities of material are added to or removed from the chip, using the layout as a template. For example, a square might be used to indicate the place on a chip where dopant is to be injected into the substrate. If two of the squares are arranged too closely together in the layout, the doped areas may interract, causing undesirable effects to the circuit.
Therefore, before preparing the layout of a semiconductor chip, a set of rules regarding the relationship of polygons in the layout is prepared. This set of rules includes a minimum separation distance between polygons.
However, minimum separation requirements become a problem when the size of polygons is changed. One common procedure used in designing the layout of a semiconductor chip is to generate a polygon on one layer of the chip by copying a polygon from another layer. The copied polygon is often changed in size, by either shrinking or growing it, before it is placed on the second layer.
Polygons are arranged on a square grid, so they may be arranged either vertically, horizontally or diagonally with respect to one another. If two polygons are arranged vertically or horizontally with respect to each another, the shortest distance between the two polygons is the distance between a side of one polygon and a side of the other polygon. If the two polygons are enlarged, the distance between the two nearest sides of the two vertically or horizontally arranged polygons will decrease. However, if two polygons are arranged diagonally, the shortest distance between the two polygons will be the distance between the corner of one polygon and the corner of the other polygon. If the two diagonally arranged polygons are enlarged to the same extent as the two vertically or horizontally arranged polygons, the distance between the corners of the two diagonally arranged polygons will decrease more than the distance between the sides of two vertically or horizontally arranged polygons.
The reason for this difference is that when the distance between sides of two vertically or horizontally spaced polygons changes by a factor of G, the distance between the corners of two diagonally spaced polygons changes by a factor of G*cosecant(θ/2), where θ is the angle formed by the two sides of the polygon that intersect to form the corner of the polygon. Because cosecants are always greater than 1 for angles greater than 0 degrees and smaller than 180 degrees, the position of the corner will change more than the position of the side changes.
The same problem occurs when a polygon is reduced in size. A polygon may have two corners that are separated by an interior distance D. If the polygon is reduced in size, the interior distance between the corners will decrease to a greater extent than the length of the sides changes. If the interior corners are not separated by the minimum distance required by the layout rules, the device that polygon represents may have undesirable properties.
As a result, growing or shrinking polygons while maintaining minimum distance requirements in the layout rules creates a problem in layout design. The prior art attempted to solve this problem in three ways, but none of them has been satisfactory.
One solution used in the prior art is to design the layout for the original polygons to eliminate the problem. For example, in order to solve the problem created by enlarging polygons, if a certain minimum separation distance of the enlarged polygons is required, one could space the original polygons much farther apart than the minimum separation distance. Then, when the polygons are enlarged, the enlarged polygons will be separated by at least the minimum separation distance. However, this solution is not satisfactory because it requires the layout rules to be larger, thereby increasing the cost of manufacture. Also, the solution in the prior art becomes unworkable if the layout rules allow arbitrarily acute angles, because the cosecant of an angle goes to infinity as the size of the angle goes to zero. A similar approach is used to shrink polygons by requiring the original polygon to be wider than necessary. Again, this solution in the prior art increases the size of the layout rules, thereby increasing the cost to manufacture. Also, this solution for shrinking polygons does not work for very small angles.
A second solution used in the prior art to solve this problem is the one used by Cadence Design Systems, Inc. in its Virtuoso® Layout Editor software. This software chamfers the corners of acute angles before they are enlarged, so that they grow no more than right angles grow. This solution limits the severity of the problem for the specific case of acute angles, but it does not solve the problem because all corners still grow more than the growth distance for the edges.
A third solution used in the prior art is to manually adjust the original polygons in the particular cases that cause problems. Thus, instead of changing the layout rules for all polygons the layout rules remain unchanged, but individual polygons are changed on a case-by-case basis. However, this solution in the prior art does not solve the problem because it still increases the layout area required and the manual intervention increases the time and cost of the layout.
Therefore, it is desirable to develop a method generating polygons that are smaller or larger than the original polygons, without requiring the rules to be changed, and without requiring manual adjustment of the layout.